1. Field of the Invention
The present invention relates to a logic processing apparatus including a semiconductor device as a component that has a chip sealed in a package, on which a logic circuit is mounted where data held in the front stage flip-flop is processed at a logic gate circuit network, and then, processed data is held in the rear stage flip-flop; particularly relates to the logic circuit in which an off-leak electric current can be reduced at the logic gate circuit network; and further relates to the semiconductor device.
2. Description of the Related Art
Recently, lower power consumption by, for example, LSI itself has been in great demand due to the improvement in mobile use of equipment. On the other hand, with the progress of a CMOS (Complementary MOS) process, in a design generation of such as 90 nm and 65 nm, off-leak electric current of the MOS transistor becomes large and power consumption thereof can not be ignored. To cope with the above consequence, the power supply has conventionally been cut off in a standby mode of operation where a clock is stopped using MT (Multi Threshold)-CMOS and others.
Patent document 1 discloses a sequence circuit that operates at high speed with low supply voltage, in which a stable and secure power down operation can be performed to reduce the power consumption. Further, Patent document 2 discloses a master-slave type flip-flop in which a function of reducing power consumption in a standby mode is provided and stored data is not lost in the standby mode.
Further, Patent document 3 discloses a semiconductor integrated circuit device including a MOS transistor, in which operation can be performed with low supply voltage in the active mode and the power consumption due to leaked electric current can be suppressed in the standby mode. Furthermore, Patent document 4 discloses an element in which the supply voltage is not applied at all to the devices other than a temporary memory element (a register element and memory, whose data is cleared when cutting off the supply voltage) in order to reduce the power consumption at the standby mode.
[Patent document 1] Japanese Published Patent Application No. H07-271477
[Patent document 2] Japanese Published Patent Application No. H11-284493
[Patent document 3] Japanese Published Patent Application No. 2000-208713
[Patent document 4] Japanese Published Patent Application No. 2001-251180
However, off-leak current is practically not able to be reduced in the active mode where the circuit is actually operating under the clock input.
Therefore, the purpose of the present invention is to provide a logic circuit, in which the off-leak electric current can be reduced in the active mode where the circuit is actually operating under the clock input; a semiconductor device that has a chip sealed in a package, on which the logic circuit is mounted; and further a logic processing apparatus including the semiconductor device as a component.